Assignment GDB Solution: CS501 Advance Computer Architecture

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CS501 Assignment No 01 Solution Fall 2017

Questions No 01 Marks (12) Write the code/instructions to implement the expression A = (B – C) + 15(D – 45) on 3, 2, 1, and 0-address machines. Questions No 02 Marks (08) Compute the total memory traffic in bytes for both instruction fetch and instruction execution for the code that implements the expression evaluation […]

CS501 Assignment 3 Solution Spring 2017

Question # 1:                                                                        12 Marks Take NUXI Problem in context (as discussed in Lecture # 24) and store the following hexadecimal values (each 4 bytes) into Little-Endian and Big-Endian memory maps. Hexadecimal Values (Most Significant to Least Significant) Little-Endian (lowest to highest address) Big-Endian (lowest to highest address) 57B1002A h     01234567 h   […]

CS501 Assignment 3 Solution Spring 2017

Question # 1 Take NUXI Problem in context (as discussed in Lecture # 24) and store the following hexadecimal values (each 4 bytes) into Little-Endian and Big-Endian memory maps. Hexadecimal Values (Most Significant to Least Significant) Little-Endian (lowest to highest address) Big-Endian (lowest to highest address) 57B1002A h 01234567 h 25267292 h AA0040BC h FEBC6012 h 1A4313D4 […]

CS501 Assignment 1 Solution Spring 2017

Question: Consider the following equation; z= 8(a-b) + 19(c-29) You have to solve this equation using the following; 3-Address instruction Solution: SUB z, a, b                  # z ← a-b MUL z, 8                     # z←8(a-b) SUB T, c, 29                # T←(c-29) MUL T, T, 19               #T←19(c-29) ADD z, z, T                   #z←(z+T) 2-Address instruction Solution: MOV z, […]

CS501 GDB Solution Feb 2015

GDB Topic: “As memory subsystem is one of the most important components of computer and the overall speed of the computer can be improved by improving the performance of memory sub-system. The performance of the memory sub-system depends on two characteristics:  Bandwidth and Latency. But, there are often subtle tradeoffs between latency and bandwidth as giving more emphasis […]

CS501 Advance Computer Architecture Assignment 2 Solution

Advance Computer Architecture (CS501) Assignment # 2    Total marks = 20                                                                                   Deadline Date = December 9, 2014 Please carefully read the following instructions before attempting assignment. Rules for Marking It should be clear that your assignment would not get any credit if: The assignment is submitted after the due date. The submitted assignment […]

CS501 Advance Computer Architecture Assignment 1 Solution Fall 2014

Question No. 1                                                                                                                 10 Marks Write assembly language instructions to execute the following expression on 0-address and 3-address machines. F = A + (B × C / D) – E Question No. 2                                                                                                                  10 Marks A compiler designer is trying to decide between two code sequences for a particular machine. The hardware designers have supplied […]

CS501 Advance Computer Architecture GDB Solution Spring 2014

Topic: In computer architecture why does a “system interface unit” provide separate queues for “read” and “write” transactions? Is it possible for a “write queue” to directly execute without interference of “read queue”?Answers must be to the point and justified with reasons. Solution: The SIU will manage separate queues for read and write transactions – taking […]

CS501 Advance Computer Architecture GDB Solution Spring 2014

All students of CS501 are directed to participate in the GDB that will be opened from 7th August 2014 to 8thAugust 2014. GDB answer via email or through MDB will not be accepted. Note: Your answer should not be more than 300 words. Topic: In computer architecture why does a “system interface unit” provide separate […]

CS501 Advance Computer Architecture Assignment 4 Solution Spring 2014

Scenarios discussion: What will be the order of “Interrupt Driven”, “DMA” and “Polling” if these two scenarios occur? 1.      Lowest impact on processor utilization to a single I/O device. Ans# If we want to be a lowest impact on Processor utilization to a single I/O device the order wil be as follows Polling Direct Memory Access Interrupt Driven. 2.      Lowest impact on […]