CS302 Digital Logic Design Assignment 1 Solution Fall 2014

Solution:

Question 1:     (10 Marks)

a) Calculate the Octal and Hexadecimal equivalent of the given binary number. Give each step of the calculation.

10111000011101101001001001001001010100

BINARY TO HEXADECIMAL

  1. 10111000011101101001001001001001010100
  2. 0010 1110 0001 1101 1010 0100 1001 0010 0101 0100
  3. 3.     2           E    1       D      A       4        9    2         5       4

Thus binary number 10111000011101101001001001001001010100 is represented in hexadecimal by 2E1DA49254.

BINARY TO OCTAL

  1. 10111000011101101001001001001001010100
  2. 010 111 000 011 101 101 001 001 001 001 001 010 100
  3.   2      7     0      3     5     5     1     1     1    1     1      2      4

Thus 10111000011101101001001001001001010100 is represented in octal by 2703551111124

b) Convert the following numbers into their equivalent BCD representation.

i)                68

BCD =  6 8 = 0110 1000

ii)               99

BCD = 9 9 = 1001 1001

c) Convert the following binary number into its equivalent decimal number by performing each step of the calculation.

1011101.10111

1.     Sum-of-Weights Method

1011101.10111 = (1×26) + (0×25) + (1×24) + (1×23) + (1×22) + (0×21) + (1×20) + (1×2-1) + (0×2-2) + (1×2-3) + (1×2-4) +(1×2-5)     

=   1×64+ 0×32 + 1×16 + 1×8 + 1×4 + 0 ×2+ 1×1 + 1×0.5  + 0 ×0.25+ 1×0.125 + 1×0.0625 + 1×0.03125

= 64+0+16+8+4+0+1+0.5+0+0.125+0.0625+0.03125

= 93.71875

Thus decimal number equivalent to 1011101.10111 is 93.71875.

Question 2: (10 Marks)

Five different timing diagrams are given below. You are required to identify the logical operation being performed by each of the following timing diagram.

Solution:

a) The logical operion  performed on (a) timing diagramare OR gate

b) The logical expression  applied on (b) timing diagram are exculisve OR gate

(c) The logical operation performed on (c) timing diagram is NAND gate.

d) The logical operation performed on (d) timing diagram is NOR gate.

e) The logical operation performed on (e)  timing diagram is AND gate

 

DOWNLOAD SOLUTION HERE
loading...