CS302 Digital Logic Design Assignment 3 solution 21 Jan 2013

Sketch the timing diagram against Q0, Q1, Q2 and Q3 and determine the counter sequence of a synchronous 4-bit binary up/down counter if the clock and UP/control inputs have waveforms as shown in figure below. The counter starts in the all 0s state and is positive edge triggered.
Solution:

98 FIGURE 9-16 A 4bit synchronous binary counter and timing

complete  solution is given in the link (example 9.4)


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