CS302 Digital Logic & Design GDB Solution Spring 2013

The topic of Graded Discussion Board:
There are three edge-triggered flip-flops namely SR, D and J-K that are used in digital logic circuits and every flip-flop has its own operation. State that how these flip-flops can have an effect on the performance of synchronous systems, and also discuss which flip-flop gives better performance? Give arguments in the support of your answer.

A concise, coherent and to the point comment is preferred over lengthy comment having irrelevant details. Your comment must not be more than 5-7 lines. Comments, posted on regular Lesson’s MDB or sent through email will not be considered in any case. Any request about such an acceptance will not be catered.
Solution: Flip-Flops are extremely important circuit elements in all synchronous VLSI circuits. They are not only responsible for the correct timing, functionality and performance of the chip, but also they and other clock distribution networks consume a significant portion of the total power of the circuit. It is estimated that the power consumption of the clock system, which consists of clock distribution networks and storage elements, is as high as 20%–45% of the total system power . Comparing to different elements in the VLSI circuits, flip-flops are the primary source of the power consumption in synchronous system. Moreover, flip-flops have a large impact on circuit speed. The performance of the Flip-Flop is an important element to determine the performance of the whole circuit. For example, the Clock-to-Q delay, Setup time and Hold time, all these parameters of the flip-flops can affect the performance of the whole circuit. Therefore, the studies on Flip-Flop become more and more in recent years.