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CS302 Digital Logic Design GDB Solution Spring 2014

The topic of Graded Discussion Board

There are three edge-triggered flip-flops namely SR, D and J-K that are used in digital logic circuits and every flip-flop has its own operation. Which flip flop will be better in performance against each factor given below?

  • Power consumption
  • Delay (in terms of output)

Give solid arguments to validate your view.

You may give another type of Flip Flop if any, that you think is better.

Edge-triggered S-R flip-flop

The basic operation is illustrated below, along with
the truth table for this type of flip-flop. The operation and truth table for
a negative edge-triggered flip-flop are the same as those for a positive
except that the falling edge of the clock pulse is the triggering edge.

 


As S = 1, R = 0.
Flip-flop SETS on the rising clock edge

Note that the S and R inputs can be
changed at any time when the clock input is LOW or HIGH (except for a very
short interval around the triggering transition of the clock) without
affecting the output. This is illustrated in the
timing diagram below:


Edge-triggered J-K flip-flop

The J-K flip-flop works very
similar to S-R flip-flop.  The only difference is that this flip-flop has NO
invalid state.  The outputs toggle (change
to the opposite state) when both J and K inputs are HIGH.  The truth table is
shown below.

Edge-triggered D flip-flop

The operations of a D flip-flop is
much more simpler.  It has only one input addition to the clock.  It is very
useful when a single data bit (0 or 1) is to be stored.  If there is a HIGH on
the D input when a clock pulse is applied, the flip-flop SETs and stores a 1.
If there is a LOW on the D input when a clock pulse is applied, the flip-flop
RESETs and stores a 0.  The truth table below summarize the operations of the
positive edge-triggered D flip-flop.  As before, the negative edge-triggered
flip-flop works the same except that the falling edge of the clock pulse is
the triggering edge.


 Pulse-Triggered
(Master-Slave) Flip-flops

The term
pulse-triggered means that data are
entered into the flip-flop on the rising edge of the clock pulse, but the
output does not reflect the input state until the falling edge of the clock
pulse.  As this kind of flip-flops are sensitive to any change of the input
levels during the clock pulse is still HIGH, the inputs must be set up prior
to the clock pulse’s rising edge and must not be changed before the falling
edge.  Otherwise, ambiguous results will happen.

The three basic types of pulse-triggered flip-flops are S-R, J-K and D.  Their
logic symbols are shown below.  Notice that they do not have the dynamic input
indicator at the clock input but have postponed
output symbols at the outputs.

The truth tables for the above
pulse-triggered flip-flops are all the same as that for the edge-triggered
flip-flops, except for the way they are clocked.  These flip-flops are also
called Master-Slave flip-flops simply
because their internal construction are divided into two sections.  The slave
section is basically the same as the master section except that it is clocked
on the inverted clock pulse and is controlled by the outputs of the master
section rather than by the external inputs.  The logic diagram for a basic
master-slave S-R flip-flop is shown below.

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