# CS302 Digital Logic Design Quiz 3 Fall 2013

Dear Students,

Quiz # 3 will start from Thursday, 30th January, 2014 and will remain open for two days the last day will be Friday, 31st January, 2014The lectures included in this quiz will befrom Lecture # 20 to Lecture # 29.

CS302 Today Quiz No 3

Question # 1 of 10 ( Start time: 11:29:09 PM )     Total Marks: 1

Bi-stable devices remain in either of their _________ states unless the inputs force the device to switch its state

Select correct option:

Ten

Eight

Three

Two

Question # 2 of 10 ( Start time: 11:30:10 PM )     Total Marks: 1

In Synchronous systems, the output of all the digital circuits changes when an enable signal is applied instead of the clock signal.

Select correct option:

True

False 228

Question # 3 of 10 ( Start time: 11:30:31 PM )     Total Marks: 1

________ flip-flops are obsolete now.

Select correct option:

Edge-triggered

Master-Slave 257

T-Flipflop

D-Flipflop

Question # 4 of 10 ( Start time: 11:31:21 PM )     Total Marks: 1

If a circuit suffers “Clock Skew “ problem, the output of circuit can’t be guarantied.

Select correct option:

True

False

Question # 5 of 10 ( Start time: 11:31:36 PM )     Total Marks: 1

Flip flops are also called _____________

Select correct option:

Bi-stable multivibrators 228

Bi-stable singlevibrators

Bi-stable dualvibrators

Bi-stable transformer

Question # 6 of 10 ( Start time: 11:33:01 PM )     Total Marks: 1

A mono-stable device only has a single stable state

Select correct option:

True 262

False

Question # 7 of 10 ( Start time: 11:33:43 PM )     Total Marks: 1

If S=1 and R=0, then for positive edge triggered flip-flop Q(t+1) = _________

Select correct option:

0

1 230

Invalid

Input is invalid

Question # 8 of 10 ( Start time: 11:34:03 PM )     Total Marks: 1

If the S and R inputs of the gated S-R latch are connected together using a ______ gate then there is only a single input to the latch. The input is represented by D instead of S or R (A gated D-Latch)

Select correct option:

AND

OR

NOT 226

XOR

Question # 9 of 10 ( Start time: 11:35:17 PM )     Total Marks: 1

In Master-Slave flip-flop the Clock signal is connected to Slave flip-flip using ________ gate

Select correct option:

AND

OR

NOT

NAND

Question # 10 of 10 ( Start time: 11:36:46 PM )   Total Marks: 1

The glitches due to “Race Condition” can be avoided by using a ___________

Select correct option:

Gated flip-flops

Pulse triggered flip-flops

Positive-Edge triggered flip-flops

Negative-Edge triggered flip-flop 267

The minimum time for which the input signal has to be maintained at the input of flip-flop is called ______ of the flip-flop.
Set-up time
Hold time 242
Pulse Interval time
Pulse Stability time (PST)
The glitches due to “Race Condition” can be avoided by using a ___________
Gated flip-flops
Pulse triggered flip-flops
Positive-Edge triggered flip-flops
Negative-Edge triggered flip-flops 267
We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), to supply the required frequency to each part of circuit, we can get help by using ___________
Using

S-R Flop-Flop
D-flipflop
J-K flip-flop
T-Flip-Flop
Once the state diagram is drawn for any sequential circuit the next step is to draw

Transiation table
Karnaugh map
Next-state table 306
Logic expression
A synchronous decade counter will have _______ flip-flops
3,
7,
4,
10
For a gated D-Latch if EN=1 and D=1 then Q(t+1) =
0,
1,
Q(t)
valid
If a circuit suffers “Clock Skew “ problem, the output of circuit can’t be guarantied.
True
false

The 74HC163 is a 4-bit Synchronous Counter.it has…………..parallel data inputs pins
2
,4
,6
,8

The _____________ input overrides the ________ input
Asynchronous, synchronous 235
Synchronous, asynchronous
Preset input (PRE), Clear input (CLR)
Clear input (CLR), Preset input (PRE)
A standard interface for programming the In-System PLD consists of
2 wire ,
4 wire 194
8 wire,
16 wire