# CS501 Advance Computer Architecture Assignment 1 Solution Spring 2014

Instructions

It should be clear that your assignment will not get any credit if:

• The assignment is submitted after the due date.
• The submitted assignment does not open or file is corrupt.
• The assignment is found to be copied from the internet.
• The assignment is found to be copied from other student.
• The assignment submitted is not according to required file format (.doc).

Objective

The objective of this assignment is:

• To assess your overall understanding of address instructions cycles which is used in almost every architecture
• To assess your overall understanding of your concept of data storage and data transmission in memory.

Note:

• The assignment should be in .doc format.
• Assignment .01 (Non Graded) covers lecture 01 – 07. You can also consult reference books for help.
• Students are advised to submit their assignment as early as possible in order to avoid any sort of inconvenience like Load shedding etc.

Question:

Students are required to perform step-by-step execution of adding two numbers and store the final result in Sum (memory).

The numbers are 0002 and 0004 residing in the memory locations 781 and 782 respectively.

Descriptions:
Step-1 is shown in Figure 1 where you can see PC = 500 indicating the instruction to be stored at address 500 in the current execution cycle. What will be the next steps and so on…

 Memory CPU register 500 1 7 8 1 500 PC 501 5 7 8 2 AC 502 2 7 8 2 1 7 8 1 IR 503 : 7 8 1 0 0 0 4 7 8 2 0 0 0 2 (STEP 1)

Figure-1

Where,

AC is Accumulator Register.

PC is Program Counter.

IR is Instruction Register.

Hints for Execution:

• First instruction 1781 means Load value stored at address 781 into accumulator register.
• Second instruction 5782 means perform addition of value stored at address 781 with value in accumulator register and store the result in accumulator register.
• Third instruction 2782 means store value of accumulator register at address 782.

Fill in the blanks with appropriate instruction and action with regarding its step

 Memory CPU register Memory CPU register 500 1 7 8 1 PC 500 1 7 8 1 PC 501 5 7 8 2 AC 501 5 7 8 2 AC 502 2 7 8 2 IR 502 2 7 8 2 IR 503 503 : : 7 8 1 7 8 1 7 8 2 (STEP 2) 7 8 2 (STEP 3) Memory CPU register Memory CPU register 500 1 7 8 1 PC 500 1 7 8 1 PC 501 5 7 8 2 AC 501 5 7 8 2 AC 502 2 7 8 2 IR 502 2 7 8 2 IR 503 503 : : 7 8 1 7 8 1 7 8 2 (STEP 4) 7 8 2 (STEP 5)
 Memory CPU register 500 1 7 8 1 PC 501 5 7 8 2 AC 502 2 7 8 2 IR 503 : 7 8 1 7 8 2 (STEP 6)

Solution:

Solution

(STEP 1)

 Memory CPU register 500 1 7 8 1 5 0 0 PC 501 5 7 8 2 AC 502 2 7 8 2 1 7 8 1 IR 503 : 7 8 1 0 0 0 4 7 8 2 0 0 0 2

(STEP 2)

 Memory CPU register 500 1 7 8 1 5 0 0 PC 501 5 7 8 2 0 0 0 4 AC 502 2 7 8 2 1 7 8 1 IR 503 : 7 8 1 0 0 0 4 7 8 2 0 0 0 2

(STEP 3)

 Memory CPU register 500 1 7 8 1 5 0 1 PC 501 5 7 8 2 0 0 0 2 AC 502 2 7 8 2 5 7 8 2 IR 503 : 7 8 1 0 0 0 4 7 8 2 0 0 0 2

(STEP 4)

 Memory CPU register 500 1 7 8 1 5 0 1 PC 501 5 7 8 2 0 0 0 6 AC 502 2 7 8 2 5 7  8 2 IR 503 : 7 8 1 0 0 0 4 7 8 2 0 0 0 2

(STEP 5)

 Memory CPU register 500 1 7 8 1 5 0 2 PC 501 5 7 8 2 0 0 0 6 AC 502 2 7 8 2 2 7 8 2 IR 503 : 7 8 1 0 0 0 4 7 8 2 0 0 0 2

(STEP 6)

 Memory CPU register 500 1 7 8 1 5 0 2 PC 501 5 7 8 2 0 0 0 6 AC 502 2 7 8 2 5 7 8 2 IR 503 : 7 8 1 0 0 0 4 7 8 2 0 0 0 6