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CS501 Advance Computer Architecture GDB Solution Spring 2014

Topic:

In computer architecture why does a “system interface unit” provide separate queues for “read” and “write” transactions?

Is it possible for a “write queue” to directly execute without interference of “read queue”?Answers must be to the point and justified with reasons.

Solution: The SIU will manage separate queues for read and write transactions – taking requests from the read queue in preference to those in the write queue. Once the processor has despatched a command to write a result to main memory, it can assume that the operation is complete and continue immediately to the following operation. Detecting read requests for data in write buffers
All read requests must be checked against transactions waiting to be written in the write buffers. This is an example of a coherence requirement – the data in the main memory is not the most recent value of the addressed location. If read requests “hit” data in the write queues, then the request must be satisfied from data in the write queue – not the data in main memory.

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