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CS501 Assignment 2 Solution Spring 2018

Questions No 1                                                                                                            Marks (7+3 = 10)

Consider the following sequence of instructions in a pipelined scenario:

  • add r2, r1, r3
  • sub r7, r2, r5
  • or r9, r6, r2
  • and r12, r7, r2
  • st r11,100(r7)
  1. Show data dependencies in the above sequence of instructions.
  2. Mention any two schemes to resolve the problems in part (a).

Questions No 2                                                                                                                      Marks (10)

Fill in the following table keeping in view logical levels of buses attached with SRC processor.  Also mention memory addressing mode for each instruction.

 

Instruction

 

RTL equivalent

 

Address Bus

<31….0>

 

Data Bus

<31….0>

 

M Read

 

 

M Write

 

Addressing Mode

load r2, [r4+8]

 

           
jnz r1, [54]

 

           
shiftr r1,r2,4

 

           
addi r3,r6, 2

 

           
store r1, r3

 

           

Memory and Register Maps:

Register Name Content
R[0] C302h
R[1] 4CB8h
R[2] 492Fh
R[3] C2EFh
R[4] 1236h
R[5] 1234h
R[6] 0020h
R[7] 2D7Fh
Memory  Address Memory Content
00000020h D2h
00000021h 96h
00000022h 49h
00000023h 2Fh
………… ………
000DC300h 44h
000DC301h 23h
000DC302h E3h
000DC303h D5h
……………. …..
000DC340h 51h
000DC341h CAh
000DC343h D5h
000DC344h E2h
…………… ……
00AB1240h 07h
00AB1241h 85h
00AB1242h E5h
00AB1243h 3Dh
…………… ……

 

Note: Address bus and Data bus values should be in hexadecimal number system.

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