CS501 Fall 2011 Final Term Feb 2012 – VU Current Paper – 08 Feb 2012

CS501 Fall 2011 Final Term Feb 2012 – VU Current Paper – 08 Feb 2012

2 Mks

RTL for no operation

Difference between CPU register and cache

What is function of platter in hard disk

Advantages and disadvantage of memory mapped cache

3 Mks

Function of valid bit in associative mapping strategy

RAID 5 and RAID 4 differences

How stack is organized , how data is stored and accessed in stack

Optical fibre , multiple mode fibre and mono mode fibre

5 Mks

Pipelining

3 x Numerical of 5 mks each

a. conversion of 0.32 decimal to binary

b. row refresh time

c. regarding hit and miss time

 

> If a DRAM has 512 rows and its fresh time is 8ms .What should e the frequency of row refresh operation on the average?(5)
> Reset defination or types (5)
> Consider a 64KB directed mapped cache with a line length of 32 bytes. Determine the number of bits in the address that refers to the byte within a cache

line. (5)
> Does DMA affect the relationship b/w the memory system and CPU? Explain with reasons. (5)

 

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