CS501 final solved paper feb 3

What function is performed by the reset operation of a processor? What are the two types of reset operations?


Reset operation is required to change the processor‘s state to a known, defined value. The two essential features of a reset instruction are clearing the control step counter and reloading the PC to a predefined value.

Hard Reset

The SRC performs a hard reset upon receiving a start (Strt) signal. This initializes the PC and the general registers.

Soft Reset

The SRC performs a soft reset upon receiving a reset (rst) signal. The soft reset results in initialization of PC only.

Q2 What do you know about Hard disk.

Solution A hard disk drive (HDD; also hard drive, hard disk, or disk drive)[2] is a devicefor storing and retrieving digital information, primarily computer data. It consists of one or more rigid (hence “hard”) rapidly rotating discs (often referred to as platters), coated with magnetic material and with magnetic heads arranged to write data to the surfaces and read it from them.

Hard drives are classified as non-volatile, random access, digital, magnetic, data storage devices. Introduced by IBM in 1956, hard disk drives have decreased in cost and physical size over the years while dramatically increasing in capacity and speed.

Hard disk drives have been the dominant device for secondary storage of data in general purpose computers since the early 1960s.[3] They have maintained this position because advances in their recording capacity, cost, reliability, and speed have kept pace with the requirements for secondary storage.[3]

Q 3

(0.23) 10 convert in base 2

Question no 4 What is meant by Packet switching

Ans lecture no 34 …(page no360)

Qusetion no 6

Classification of fiber optics mode multimode and mono mode?


Multimode…… this fiber has large diameter when light is injected,it is disperses,so the effective data rate is dicreses.

Mono mode

Its diameter is very small.So dispersion ios small and data rate is very high.

Question no 7

Considered a 64kb direct maped catch with a line length of 32bytes

a determine the number of bits in the address that refer to the byte withen a cache line.

b determine the number of bits in the address required to select the cache line.

Solution (lecture no 41 ) page 348 o

Question no 8

If a DRAM has 512 rows and its fresh time is 9ms .What shoul be the frequency of row refresh operation on the average?


Refresh time =9ms

Number of rows =512

Therefore we have to do 512 rows refresh operation in 9ms interval.in other words one row refresh operation every( 9*10-³)/512=1.76*10 second

Question Structural RTL for not instruction not ra ,rb

Solution in lecture no 13

Question why we use matrix in decoder

Msqs were from mostly past papers