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CS501 VU Assignment No. 2 Spring 2012 Solution

What will be the logic levels on the external FALCONA buses when each of the given FALCONA instruction is executing on the processor? Complete the table given. All numbers are in the decimal number.

Describe in your own words of how you completed the given table, instruction
by instruction?

In this table the second column contains the RTL descriptions of the instructions. We have to specify the address bus and data bus contents for each instruction execution. The detail of the every instruction is given below.

1) Load instruction placed the contents of register r3+11 on the address bus. From register map we can see that the contents of r3 are 1123h. Now contents of r3 are added with displacement value 12 in decimal . 1123h+ Bh = 112Eh.
Now for load instruction, the contents of memory location at address 112Eh. will be placed on the data bus. From the memory map that given the memory contents of location 112Eh are not shown we spouse this memory location contains 0587h. Now to read this data from this location, MRead control signal will be activated shown by 1 in the next column and MWrite would be 0.
2) For the 2nd instruction. In this instruction, only registers are involved so there is no need to activate external bus. So data bus, address bus and control bus columns will contain ‘?’ or ‘unknown’. After adding the displacement 30 in the contents of R3 the result will be store in R2.
3) The next instruction is jump. Here PC is incremented by the jump offset, which is 50 in this case. As before, the external bus will remain inactive and control signals will be zero.
4) The next instruction is store. Its RTL description is given. For store instruction, the register contents have to be placed at memory location addressed by R [4] +18. As this is a memory write operation, the MWrite will be 1 and MRead will be zero. Now the effective address will be determined by adding the contents of R [4] with the displacement value 18 after its conversion to the hexadecimal. The resulting effective address would be C516h. From the memory map that given the memory contents of location C516h are not shown we spouse this memory location contains 0256h.
5) In the sub instruction after subtraction the contents of R6 from R5 the result will be store in R3. the external bus will remain inactive and control signals will be zero.
6) In shift instruction, after shifting the contents of register R6 to right the result will be store in the R1. In this case the buses and control signals also will be inactive.
7) In mov instruction the contents of register R1 will be copy to the register R4 , and the buses and control signals will remain inactive.
8) In jz , its conditional jump and it will only executed when the condition will true, and in this instruction we can see that only register and PC is involved so the buses and control signal will be inactive.

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