1. The following table shows a partial summary of the ISA for the SRC. Write an assembly language program using the SRC assembly language to evaluate the
Z= (7 + 16a) – (8b – c)
Note: a, b and c are names of memory locations. Your program should not change the source operands. Do not worry about the contents of a and b. There is no
need to worry about assembler directives. Comments in your code may be helpful.
Find the bandwidth of a memory system that has a latency of 30ns, a pre charge time of 10ns and transfers 3 bytes of data per access .
2. Explain the Direct Mapping cache strategy.
3. How many platters are required for a 40GB disk if there are 1024 bytes/sector, 2048 sectors per track and 4096 tracks per platter?
1. What do you understand by RAID 2?
2. Give an example for the logic design level, circuit level and mask level abstractions of digital design.
3. Differenciate between Spatial Locality And Temporal Locality .
4. Suppose an I/O system with a single disk gets (on average) 200 I/O requests/second. Assume that average time for a disk to service an I/O request is 4ms.
What is the utilization of the I/O system?
1. Which term do we use to describe a “storage systems” resilience to disk failure through the use of multiple disks and by the use of data distribution and
2. Differentiate between CPU register and Cache Memory.
3. Write one advantage and one disadvantage of cache design.
4. What is the format of a 0-address instruction set?
How many drives do you need a minimum to form RAID 0?